Parallel Counter Formulation using a Generator Polynomial Expansion
نویسنده
چکیده
Parallel counters have been studied for several decades as a component in fast multipliers and multioperand adder circuits. Efficient design of these functional units can produce fast & efficient multipliers and signal processors. Proposed in this paper is a GF(2) generator polynomial expansion that can be used to specify parallel counters. The mathematical formalism provides a general way of describing parallel counters. Furthermore, the expansion suggests a gate level implementation for parallel counters.
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تاریخ انتشار 2012